Image sensor with a capacitive storage node linked to transfer gate

Abstract

A CMOS imaging system with increased charge storage capacitance of pixels yet decreased physical size, kTC noise and active area. A capacitor is linked to the transfer gate and provides a storage node for a pixel, allowing for kTC noise reduction prior to readout. The pixel may be operated with the shutter gate on during the integration period to increase the amount of time for charge storage by a pixel.

Claims

1 . A method of operating a pixel of an image sensor comprising: accumulating charge in a photosensor; transferring said charge from said photosensor to a storage device; transferring said charge from said storage device to a floating diffusion node; and reading out the charge residing in said floating diffusion node. 2 . The method of claim 1 , wherein said storage device comprises a storage element residing above a substrate containing said pixel and a storage node within said substrate. 3 . A method of operating a plurality of pixels of an image sensor comprising: accumulating a first charge in a first photosensor; transferring said first charge from said first photosensor to a first storage device; transferring said first charge from said first storage device to a floating diffusion node; reading out the first charge from said floating diffusion node; accumulating a second charge in a second photosensor; transferring said second charge from said second photosensor to a second storage device; transferring said second charge from said second storage device to said floating diffusion node; and reading out the second charge from said floating diffusion node. 4 . The method of claim 3 , wherein a portion of said first and second storage devices reside above a substrate in which the first and second photosensors reside. 5 . The method of claim 3 further comprising the act of sharing said floating diffusion node with a third and fourth pixel, wherein said floating diffusion node is reset, said third pixel accumulates a third charge in a third photosensor, transfers said third charge from said third photosensor to a third storage device, transfers said third charge from said third storage device to said floating diffusion node and reads out the third charge from said floating diffusion node; and wherein said floating diffusion node is reset, said fourth pixel accumulates a fourth charge in a fourth photosensor, transfers said fourth charge from said fourth photosensor to a fourth storage device, transfers said fourth charge from said fourth storage device to said floating diffusion node and reads out the fourth charge from said floating diffusion node. 6 . The method of claim 3 , wherein a readout circuit outputs the first and second charges by: turning on a first transfer gate of a first pixel to transfer the first charge to the floating diffusion node, and turning on a row select transistor; and turning on a second transfer gate of a second pixel after the readout of said first pixel to transfer the second charge to said floating diffusion node, and turning on said row select transistor. 7 . The method of claim 6 , wherein said transferring steps occur on half clock cycles. 8 . A method of reading charge from pixels of an image sensor comprising: turning on a first transfer gate transistor associated with a first pixel to transfer a first charge to a floating diffusion node; turning on a row select transistor connected to the floating diffusion node to output the first charge from said floating diffusion node; and while the row select transistor remains on, turning on a second transfer gate transistor associated with a second pixel to transfer a second charge to said floating diffusion node and to output the second charge from said floating diffusion node. 9 . The method of claim 8 , wherein the transfer of said first and second charges occur on a respective half clock cycle. 10 . The method of claim 8 , wherein said first transfer gate remains on during an integration period. 11 . A pixel circuit for use in an imaging device, said pixel circuit comprising: a photosensor for generating charge during an integration period; a shutter transistor connected to said photosensor to transfer charge from said photosensor; a storage capacitor connected to said shutter transistor to receive said charge transferred by said shutter transistor; a transfer gate connected to said storage capacitor to transfer charge from said storage capacitor; a floating diffusion node connected to said transfer gate to receive said charge from said transfer gate; and a readout circuit connected to said floating diffusion node to output the charge accumulated at the floating diffusion node. 12 . The circuit of claim 11 , wherein said readout circuit further comprises: a reset transistor connected to said floating diffusion node for resetting the voltage on the floating diffusion node; a source-follower transistor connected to said reset transistor for receiving charge from the floating diffusion node; and a row select transistor connected to said source-follower transistor for outputting a signal produced by said source follower transistor. 13 . The circuit of claim 11 , wherein said capacitor is formed above a substrate in which the floating diffusion node is formed. 14 . The circuit of claim 13 , wherein said capacitor is a polypropylene capacitor. 15 . The circuit of claim 11 , wherein said shutter transistor is an electronic shutter for said pixel. 16 . The circuit of claim 11 , wherein said shutter transistor remains on during the integration period. 17 . The circuit of claim 11 , wherein said pixel is a CMOS pixel. 18 . The circuit of claim 11 , wherein said pixel comprises five transistors. 19 . A pixel circuit for use in an imaging device, said pixel circuit comprising: a plurality of photosensors for generating charge during an integration period; a plurality of shutter transistors, each shutter transistor connected to and transferring charge from a respective photosensor; a plurality of storage nodes, each node coupled to a respective shutter transistor and storing charge transferred by a respective one of said plurality of photosensors; a plurality of transfer gates, each transfer gate connected to and transferring charge from a respective storage node; a floating diffusion node connected to said plurality of transfer gates for receiving charge from said transfer gates; and a readout circuit connected to said floating diffusion node to output charge accumulated at the floating diffusion node. 20 . The circuit of claim 19 wherein said readout circuit further comprises a reset transistor connected to said floating diffusion node for resetting the voltage on the floating diffusion node prior to receiving charge from a respective one said plurality of transfer gates. 21 . The circuit of claim 19 , wherein said storage nodes comprise capacitors formed above a substrate in which the floating diffusion node is formed. 22 . The circuit of claim 21 , wherein said capacitors are polypropylene capacitors. 23 . The circuit of claim 19 , wherein said shutter transistors operate as electronic shutters for said pixel. 24 . The circuit of claim 19 , wherein said shutter transistors remain on during the integration period. 25 . The circuit of claim 19 , wherein said pixel is a CMOS pixel. 26 . The circuit of claim 19 , wherein said pixel is a five transistor pixel. 27 . A pixel circuit for use in an imaging device, said pixel circuit comprising: a photosensor for generating charge during an integration period; a shutter transistor connected to said photosensor to transfer charge from said photosensor; a storage capacitor connected to said shutter transistor to receive said charge transferred by said shutter transistor; a transfer gate connected to said storage capacitor to transfer charge from said storage capacitor; a floating diffusion node connected to said transfer gate to receive said charge from said transfer gate; a reset transistor connected to said floating diffusion node for resetting the voltage on the floating diffusion node; a source-follower transistor connected to said reset transistor for receiving charge from the floating diffusion node; and a row select transistor connected to said source-follower transistor for outputting a signal produced by said source follower transistor. 28 . The circuit of claim 27 , wherein a plurality of pixel circuits share said floating diffusion node, reset transistor, source follower transistor, and row select transistor. 29 . The circuit of claim 27 , wherein said pixel is a CMOS pixel. 30 . A pixel sensor array comprising: a plurality of pixels, each pixel comprising: a photosensor for generating charge during an integration period; a shutter transistor connected to said photosensor to transfer charge from said photosensor; a storage capacitor connected to said shutter transistor to receive said charge transferred by said shutter transistor; a transfer gate connected to said storage capacitor to transfer charge from said storage capacitor; a floating diffusion node connected to said transfer gate to receive said charge from said transfer gate; and a readout circuit connected to said floating diffusion node to output the charge accumulated at the floating diffusion node. 31 . The array of claim 30 wherein said readout circuit further comprises a reset transistor connected to said floating diffusion node for resetting the voltage on the floating diffusion node. 32 . The array of claim 30 , wherein said capacitor is formed above a substrate in which the floating diffusion node is formed. 33 . The array of claim 30 , wherein said shutter transistor is an electronic shutter. 34 . The array of claim 30 , wherein the shutter transistor remains on during an integration period. 35 . The array of claim 30 , wherein said pixel is a CMOS pixel. 36 . An imaging system pixel comprising: a processor; and an imaging device comprising an array of pixels, coupled to said imaging system comprising: a photosensor for generating charge during an integration period; a shutter transistor connected to said photosensor to transfer charge from said photosensor; a storage capacitor connected to said shutter transistor to receive said charge transferred by said shutter transistor; a transfer gate connected to said storage capacitor to transfer charge from said storage capacitor; a floating diffusion node connected to said transfer gate to receive said charge from said transfer gate; and a readout circuit connected to said floating diffusion node to output the charge accumulated at the floating diffusion node. 37 . The system of claim 36 , wherein said capacitor is formed above a substrate in which the floating diffusion node is formed. 38 . The system of claim 37 , wherein said capacitor is a polypropylene capacitor. 39 . The system of claim 36 , wherein said shutter transistor is an electronic shutter. 40 . The system of claim 36 , wherein said shutter transistor remains on during the integration period. 41 . The system of claim 36 , wherein said imaging system is a CMOS imaging system. 42 . An imaging system comprising: a processor; and an imaging device comprising an array of pixels, coupled to said imaging system comprising: a plurality of photosensors for generating charge during an integration period; a plurality of shutter transistors, each shutter transistor connected to and transferring charge from a respective photosensor; a plurality of storage capacitors, each capacitor coupled to a respective shutter transistor and storing charge transferred by a respective one of said plurality of photosensors; a plurality of transfer gates, each transfer gate connected to and transferring charge from a respective storage capacitor; a floating diffusion node connected to said plurality of transfer gates for receiving charge from said transfer gates; and a readout circuit connected to said floating diffusion node to output charge accumulated at the floating diffusion node. 43 . The system of claim 42 , wherein a number of said plurality of photosensors is two photosensors. 44 . The system of claim 42 , wherein a number of said plurality of photosensors is four photosensors. 45 . The system of claim 42 , wherein said shutter transistor is an electronic shutter. 46 . The system of claim 42 , wherein said shutter transistor remains on during the integration period. 47 . The system of claim 42 , wherein said capacitors are polypropylene capacitors. 48 . The system of claim 42 , wherein said imaging system is a CMOS imaging system.
FIELD OF THE INVENTION [0001] The invention relates generally to improving the charge storage capacity of an imager pixel. BACKGROUND OF THE INVENTION [0002] An imager, for example, a CMOS imager includes a focal plane array of pixel cells; each cell includes a photosensor, for example, a photogate, photoconductor or a photodiode overlying a substrate for producing a photo-generated charge in a doped region of the substrate. A readout circuit is provided for each pixel cell and includes at least a source follower transistor and a row select transistor for coupling the source follower transistor to a column output line. The pixel cell also typically has a floating diffusion node, connected to the gate of the source follower transistor. Charge generated by the photosensor is sent to the floating diffusion node. The imager includes a transistor for transferring charge from the photosensor to a storage node, and a transistor for transferring charge from the storage node to the floating diffusion node. The imager also includes a transistor to reset the floating diffusion node. [0003] FIG. 1 illustrates a block diagram of a CMOS imager device 908 having a pixel array 200 with each pixel cell being constructed as described above. Pixel array 200 comprises a plurality of pixels arranged in a predetermined number of columns and rows. The pixels of each row in array 200 are all turned on at the same time by a row selected line, and the pixels of each column are selectively output by respective column select lines. A plurality of rows and column lines are provided for the entire array 200 . The row lines are selectively activated in sequence by the row driver 210 in response to row address decoder 220 and the column select lines are selectively activated in sequence for each row activation by the column driver 260 in response to column address decoder 270 . Thus, a row and column address is provided for each pixel. The CMOS imager is operated by the control circuit 250 , which controls address decoders 220 , 270 for selecting the appropriate row and column lines for pixel readout, and row and column driver circuitry 210 , 260 which apply driving voltage to the drive transistors of the selected row and column lines. The pixel output signals typically include a pixel reset signal, V rst taken off of the floating diffusion node when it is reset and a pixel image signal, V sig , which is taken off the floating diffusion node after charges generated by an image are transferred to it. The V rst and V sig signals are read by a sample and hold circuit 265 and are subtracted by a differential amplifier 267 , which produces a signal V rst −V sig for each pixel, which represents the amount of light impinging on the pixels. This difference signal is digitized by an analog to digital converter 275 . The digitized pixel signals are then fed to an image processor 280 to form a digital image. The digitizing and image processing can be on or off the imager chip. [0004] Imager pixels, including CMOS imager pixels, typically have low signal to noise ratios and narrow dynamic range because of their inability to fully collect, transfer and store the electric charge collected by the photosensitive area of the photosensor. In addition, the pixels are subject to kTC noise, which is thermal dependant noise generated during the reset of the pixel. The kTC noise refers to the random variations of voltage during the reset of a diffusion area or capacitor. [0005] Since the size of the pixel electrical signal is very small due to the collection of photons in the photo array, the signal to noise ratio and dynamic range of the pixel should be as high as possible. In addition, the use of additional gates to increase the functional operations of the pixel (i.e., electronic shuttering) increases the size of the pixel or reduces the fill factor of the pixel. There is needed, therefore, an improved pixel photosensor for use in an imager with decreased noise and size, and larger storage capacitance which occupies a relatively small area in the silicon. BRIEF SUMMARY OF THE INVENTION [0006] The present invention provides increased storage capacity for an imager. In a first embodiment of the imager, e.g., a CMOS imager, each pixel has a global electronic shutter that transfers the image electrons to a storage node before further transferring these electrons to the pixel's floating diffusion node. The storage node is capacitively linked to the shutter clock to increase the storage capacitance of the storage node and to clock (i.e., drive) charges by increasing and decreasing the potential at the storage node. By including an additional storage node in the pixel, the floating diffusion node can be reset and readout prior to charge transference to the floating diffusion node, which allows for double sampling and a reduction of kTC noise. The amount of charge in which a pixel can store also increases since the storage node has a greater charge storage capacitance than the floating diffusion node. [0007] In a second embodiment, two pixels having respective storage nodes share a floating diffusion node and reset and readout circuitry. In addition to an increased storage capacity, the charge generating area of the pixels is increased because the area normally devoted to a second floating diffusion node, and reset and readout circuitry is now shared by the two pixels. Since two pixels share a floating diffusion node and reset and readout circuitry, a shutter clock for the first pixel is clocked onto the floating diffusion node to correctly readout and output an image. Once the readout and output of the first pixel occurs, the floating diffusion node is reset and the shutter clock for the second pixel is clocked onto the same floating diffusion node for output in the same fashion as the first pixel. [0008] In a third embodiment, four pixels using the storage node described above share a floating diffusion node and reset and readout circuitry. This further increases the charge generating area of the pixels by using the area formerly designated for use by three floating diffusion nodes and associated reset and readout circuitry to increase the charge generating area of each pixel. Since four pixels share a floating diffusion node, and reset and readout circuitry, the two pixels sharing a column or row are output during the same clock cycle. This occurs by clocking the first pixel onto the floating diffusion node and resetting the floating diffusion node on a first half clock cycle. The second pixel is subsequently clocked onto the floating diffusion node during a second half clock cycle for readout and output. This operation is repeated for output of the third and fourth pixel, each of which is output on a half cycle of the second clock cycle. [0009] In addition, a function that may be included to further increase the performance of the CMOS imager embodiments is operating the CMOS pixel with the shutter gate of the imager in an open position during a charge integration period. Having the gate open during the integration period allows additional time for a charge to be collected and transferred to the storage node. As a result, the size of the shutter gates can be reduced and the pixel has a larger charge storage capacitance. BRIEF DESCRIPTION OF THE DRAWINGS [0010] The foregoing and other advantages and features of the invention will become more apparent from the detailed description of exemplary embodiments provided below with reference to the accompanying drawings in which: [0011] FIG. 1 is a block diagram of a conventional CMOS imager; [0012] FIG. 2 is a schematic circuit diagram of an exemplary five transistor pixel according to a first embodiment of the invention; [0013] FIG. 3 is a schematic circuit diagram of an exemplary circuit in which two pixels share readout circuitry according to a second embodiment of the invention; [0014] FIG. 4 is a schematic circuit diagram of an exemplary circuit in which four pixels share readout circuitry according to a third embodiment of the invention; [0015] FIG. 5 is a timing diagram of charge storage integration according to a first embodiment of the invention; [0016] FIG. 6 is a timing diagram of charge readout according to a first embodiment of the invention; [0017] FIG. 7 is a timing diagram of charge readout according to a second embodiment of the invention; [0018] FIG. 8 is a timing diagram of charge readout according to a third embodiment of the invention; [0019] FIG. 9 is a top down diagram of an exemplary pixel circuit according to a first embodiment of the invention; [0020] FIG. 10 is a top down diagram of an exemplary pixel circuit according to a second embodiment of the invention; [0021] FIG. 11 is a top down diagram of an exemplary pixel circuit according to a third embodiment of the invention; and [0022] FIG. 12 is a diagram of a processing system which employs a CMOS imager having a pixel array in accordance with an embodiment of the invention. DETAILED DESCRIPTION OF THE INVENTION [0023] In the following detailed description, reference is made to the accompanying drawings, which are a part of the specification, and in which is shown by way of illustration various embodiments whereby the invention may be practiced. These embodiments are described in sufficient detail to enable those skilled in the art to make and use the invention. It is to be understood that other embodiments may be utilized, and that structural, logical, and electrical changes, as well as changes in the materials used, may be made without departing from the spirit and scope of the present invention. Additionally, certain processing steps are described and a particular order of processing steps is disclosed; however, the sequence of steps is not limited to that set forth herein and may be changed as is known in the art, with the exception of steps or acts necessarily occurring in a certain order. [0024] The terms “wafer” and “substrate” are to be understood as interchangeable and as including silicon, silicon-on-insulator (SOI) or silicon-on-sapphire (SOS), doped and undoped semiconductors, epitaxial layers of silicon supported by a base semiconductor foundation, and other semiconductor structures. Furthermore, when reference is made to a “wafer” or “substrate” in the following description, previous process steps may have been utilized to form regions, junctions or material layers in or on the base semiconductor structure or foundation. In addition, the semiconductor need not be silicon-based, but could be based on silicon-germanium, germanium, gallium arsenide, or other known semiconductor materials. [0025] The term “pixel” refers to a photo-element unit cell containing a photoconversion device or photosensor and transistors for processing an electrical signal from electromagnetic radiation sensed by the photoconversion device. The pixels discussed herein are illustrated and described as inventive modifications to four transistor (4T) pixel circuits for the sake of example only. It should be understood that the invention may be used with other pixel arrangements having fewer (e.g., 3T) or more (e.g., 5T) than four transistors. Although the invention is described herein with reference to the architecture and fabrication of one pixel, it should be understood that this is representative of a plurality of pixels in an array of an imager device. In addition, although the invention is described below with reference to a CMOS imager, the invention has applicability to any solid state imaging device having pixels. The following detailed description is, therefore, not to be taken in a limiting sense, and the scope of the present invention is defined only by the appended claims. [0026] FIG. 2 illustrates an exemplary circuit 300 for a pixel of a CMOS imager according to a first exemplary embodiment of the invention. The pixel includes a photosensor, e.g. a photodiode 302 , shutter gate transistor 304 , storage node 324 , capacitor 306 , transfer gate transistor 310 , a floating diffusion node 322 , and a reset and readout circuit 315 including reset transistor 314 , source follower transistor 320 and row select transistor 318 . [0027] FIG. 9 is a top down illustration of circuit 300 showing photodiode 302 connected to shutter gate transistor 304 . Shutter gate transistor 304 is connected to storage capacitor 306 via a global shutter line 305 . Capacitor 306 may be, for example, a polypropylene capacitor and is formed above the substrate containing the other element of circuit 300 . Capacitor 306 is connected to storage node 324 . Storage node 324 is connected to transfer gate transistor 310 which is coupled to the readout circuit 315 via floating diffusion node 322 . Tying storage capacitor 306 to shutter gate transistor 304 drives storage node 324 to a high potential when transferring charge from the photodiode 302 to the storage node 324 . Reducing the voltage on storage node 324 allows charge transfer from the storage node 324 to the floating diffusion node 322 . [0028] The pixel 300 illustrated in FIGS. 2 and 9 is formed on a semiconductor substrate and utilizes intermediate storage node 324 via capacitor 306 for storing charge from photodiode 302 . As photodiode 302 generates signal charge in response to incident light, the charge is transferred via the shutter gate transistor 304 to storage node 324 connected to the capacitor 306 . [0029] The timing of charge storage in capacitor 306 occurs by first resetting storage node 324 , resetting photodiode 302 , and resetting storage node 324 a second time, which is illustrated in FIG. 5 . Alternatively, the pixel could be processed to have the potential under the shutter gate transistor 304 lower than the potential under the transfer gate transistor 310 when both gates are on such that storage node 324 could be reset by holding the transfer gate transistor 310 high (as depicted by the dotted line) and cycling the shutter gate transistor 304 . In either case, the gate of reset transistor 314 should be high during reset of storage node 324 to ensure that the floating diffusion node 322 is maintained at a high potential. [0030] Subsequent to storage node's 324 second reset, charge received from photodiode 302 is transferred to storage capacitor 306 during a charge integration period; however, charge received from photodiode 302 could also be transferred to storage capacitor 306 after the charge integration period. The storage capacitor 306 permits a greater amount of charge to be stored at node 324 . Consequently, the capacitive storage of the pixel is increased. [0031] In addition, because the charge transferred from photodiode 302 is stored in a storage node 324 , the floating diffusion node 322 can be reset during the same frame the image is captured. This permits a correlated double sampling operation resulting in a sharper image. The charge residing at storage node 324 is subsequently transferred to the floating diffusion node 322 by the transfer gate 310 , where the charge is applied to the gate of source follower transistor 320 for readout through row select transistor 318 . [0032] FIG. 6 illustrates an output timing diagram for circuit 300 ( FIG. 2 ) during pixel readout. The row select transistor 318 is pulsed, turning on the row select transistor 318 . Reset transistor 314 is briefly turned on, thereby resetting floating diffusion node 322 to a predetermined voltage. The charge on the floating diffusion node 322 is applied to the gate of source follower transistor 320 , which is translated to a voltage and subsequently sampled by sample and hold circuitry, where a pulse in SHR represents a time when the reset voltage is stored on a sample and hold capacitor. [0033] Charge stored in storage capacitor 306 is then transferred to floating diffusion node 322 by turning on transfer gate transistor 310 . The charge on the floating diffusion node 322 is applied to the gate of source follower transistor 320 , which is translated to a voltage and subsequently sampled by sample and hold circuitry for readout, where a pulse in SHS represents a time when the signal voltage is stored in a sample and hold capacitor. [0034] The FIG. 2 circuit 300 operates using a global electronic shutter, for example, shutter gate 304 , which allows an input signal, i.e., incident light, to be applied simultaneously across an imager array so each row of pixels in the array acquires the charge from respective photodiodes at the same time. When acquiring an image, the integration cycle for each row is the same. Once the image has been acquired, the charge from each pixel is transferred to a storage node for readout. The readout occurs row-by-row; however, the input for each row's image is captured simultaneously. Thus, the actual time in which signal acquisition begins and ends is different from row to row. Consequently, each row in the array is integrated separately, but the time that each row acquires a signal is the same. [0035] The FIG. 2 circuit 300 employs one floating diffusion node 322 per pixel. FIG. 3 illustrates a second exemplary embodiment of the invention in which two pixels share a floating diffusion node 430 and reset and readout circuitry 432 , which includes a reset transistor 434 , source follower transistor 436 and row select transistor 438 . The illustrated circuit 400 includes two pixels, each including respective photodiodes 401 , 402 , shutter gate transistors 404 , 416 , storage nodes 410 , 426 , capacitors 408 , 420 , and transfer gate transistors 414 , 428 . The two pixels share readout circuit 432 and floating diffusion node 430 . A single output line out is provided for the two pixels. [0036] FIG. 10 is a top down illustration of circuit 400 showing photodiode 401 connected to shutter gate transistor 404 . Shutter gate transistor 404 is connected to storage capacitor 408 via a first shutter line 405 . Capacitor 408 is connected to storage node 410 . Storage node 410 is connected to transfer gate transistor 414 for charge transference to the circuit 432 for a first charge readout. Photodiode 402 is connected to shutter gate transistor 416 . Shutter gate transistor 416 is connected to storage capacitor 420 via a second shutter line 425 . Capacitor 420 is connected to storage node 426 . Storage node 426 is connected to transfer gate transistor 428 for charge transference to the same shared reset and readout circuit 432 used by the first pixel for a second charge readout. [0037] Because multiple pixels are being readout by the same circuit 432 to display an image, pixel timing is set to allow readout of each pixel based on its predetermined position in the imager array. When the two pixels sharing circuit 432 reside in the same row or column, two transfer gates 414 , 428 are utilized to clock the respective pixel signals into the floating diffusion node 430 at the required timing. For example, the transfer gate 414 of the first pixel is turned on, transferring the charge residing in the storage node 410 to the floating diffusion node 430 . This charge is then readout by turning the row select transistor 438 on. Once the row select transistor 438 and source follower transistor 436 outputs the charge, the floating diffusion node 430 is reset by turning the reset transistor 434 on. Once the floating diffusion node 430 is reset, the charge from the second pixel can be readout using the same technique. As a result, the row select transistor 438 would be on for both transfers in order to readout both pixels within in a cycle. [0038] FIG. 7 illustrates the output timing of circuit 400 ( FIG. 3 ) during pixel readout. The row select transistor 438 is pulsed on. Reset transistor 434 is briefly turned on, thereby resetting floating diffusion node 430 to a predetermined voltage. The charge on the floating diffusion node 430 is applied to the gate of source follower transistor 436 , which is translated to a voltage and subsequently sampled by sample and hold circuitry, where a pulse in SHR represents the time when the reset voltage is stored on the sample and hold capacitor. [0039] Charge stored in storage capacitor 410 is then transferred to floating diffusion node 430 by turning transfer gate transistor 414 on. The charge on the floating diffusion node 430 is applied to the gate of source follower transistor 436 , which is translated to a voltage and subsequently sampled by sample and hold circuitry, where a pulse in SHS represents the time when the signal voltage is stored in the sample and hold capacitor. Photodiode 401 is subsequently reset. [0040] The readout technique is then repeated to readout a charge accumulated by the second pixel, and results in charge transference from capacitor 420 through transfer gate transistor 428 and onto the same floating diffusion node 430 for readout. Readout from each respective pixel signal occurs in a single output cycle. Consequently, the readout of pixel circuit 400 uses two clock cycles. [0041] The circuit 400 has the same benefits as circuit 300 , and additionally allows for the use of a photodiode with increased charge generation area since two photodiodes 401 , 402 share a floating diffusion node and additional circuitry is not required to couple the signals from nodes 410 , 426 to the common floating diffusion node 430 . [0042] FIG. 4 illustrates a pixel circuit 500 of a CMOS imager according to a third exemplary embodiment of the invention. In this embodiment, four pixels share a floating diffusion node 590 , and reset and readout circuit 585 . The four pixels comprise respective photodiodes 501 , 520 , 540 , 560 , shutter gate transistors 502 , 522 , 542 , 562 , storage nodes 505 , 525 , 545 , 565 , capacitors 506 , 526 , 546 , 566 , transfer gate transistors 510 , 530 , 550 , 570 , and each pixel shares reset and readout circuit 585 , which includes reset transistor 588 , source follower transistor 584 and row select transistor 582 . [0043] FIG. 11 is a top down illustration of circuit 500 showing photodiode 501 connected to shutter gate transistor 502 . Shutter gate transistor 502 is connected to storage capacitor 506 via a first shutter line 504 . Capacitor 506 is connected to storage node 505 . Storage node 505 is connected to transfer gate transistor 510 for charge transference to readout circuit 585 via floating diffusion node 590 for a first charge readout. Photodiode 520 is connected to shutter gate transistor 522 . Shutter gate transistor 522 is connected to storage capacitor 526 via a second shutter line 524 . Capacitor 526 is connected to storage node 525 . Storage node 525 is connected to transfer gate transistor 530 for charge transference to the readout circuit 585 via floating diffusion node 590 during a second charge readout. [0044] Photodiode 540 is connected to shutter gate transistor 542 . Shutter gate transistor 542 is connected to storage capacitor 546 via a third shutter line 544 . Capacitor 546 is connected to storage node 545 . Storage node 545 is connected to transfer gate transistor 550 for charge transference to the readout circuit 585 via floating diffusion node 590 during a third charge readout. Photodiode 560 is connected to shutter gate transistor 562 . Shutter gate transistor 562 is connected to storage capacitor 566 via a fourth shutter line 564 . Capacitor 566 is connected to storage node 565 . Storage node 565 is connected to transfer gate transistor 570 for charge transference to the readout circuit 585 via floating diffusion node 590 during a fourth charge readout. [0045] Because four pixels are being readout by the same readout circuit 585 , the readout process is similar to the readout of the second embodiment ( FIG. 3 ) but altered to output twice the number of signals than that of the second embodiment. When the readout circuit 585 reads out an image using pixels that reside in the same row or column, the two of the four transfer gates ( 510 and 550 or 530 and 570 ) associated with a corresponding photosensor ( 501 and 540 or 520 and 560 ) are utilized to clock a pixel signal onto the floating diffusion node 590 with the required timing. [0046] FIG. 8 illustrates the output timing of circuit 500 ( FIG. 4 ) during pixel readout. The row select transistor 582 is pulsed on by a row select signal. Reset transistor 588 is briefly turned on, thereby resetting floating diffusion node 590 to a predetermined voltage. The charge on the floating diffusion node 590 is applied to the gate of source follower transistor 584 , which is translated to a voltage and subsequently sampled by sample and hold circuitry, where a pulse in SHR represents the time when the reset voltage is stored on the sample and hold capacitor. [0047] Charge stored in storage capacitor 526 is then transferred to floating diffusion node 590 by turning transfer gate transistor 530 on. The charge on the floating diffusion node 590 is applied to the gate of source follower transistor 584 , which is translated to a voltage and subsequently sampled by sample and hold circuitry, where a pulse in SHS represents the time when the signal voltage is stored in the sample and hold capacitor. the values in the sample and hold capacitors can be subtracted to obtain a differential signal readout (V rst −V sig ). Photodiode 520 is subsequently reset. [0048] The readout technique is then repeated to readout each signal from the remaining pixels of circuit 500 . Charge accumulated by capacitor 506 from photodiode 501 in response to its respective pixel signal is transferred from capacitor 506 through transfer gate transistor 510 and onto floating diffusion node 590 . Charge accumulated by capacitor 546 from photodiode 540 in response to its respective pixel signal is transferred from capacitor 546 through transfer gate transistor 550 and onto floating diffusion node 590 . Charge accumulated by capacitor 566 from photodiode 560 in response to its respective pixel signal is transferred from capacitor 566 through transfer gate transistor 570 and onto floating diffusion node 590 . [0049] The readout timing of circuit 500 uses two clock cycles; however, since four pixels are being output in the two clock cycles, the readout of each pixel signal occurs on a half clock cycle allowing the readout of two pixels per output clock cycle. The row select transistor 582 is on for all four transfers. [0050] The circuit 500 illustrated in FIG. 4 operates similarly to circuit 400 illustrated in FIG. 3 ; however, four adjacent photodiodes 501 , 520 , 540 , 560 share the floating diffusion node 590 and reset and readout circuit 585 . With four pixels sharing circuitry in the circuit 500 , the photodiode areas can be further increased due to the reduction in the number of floating diffusion nodes, and reset transistors and readout circuits. [0051] Charge storage capacity of each of the exemplary embodiments depicted in FIGS. 2-11 can be further increased by leaving the shutter gate on during the photodiode integration period. By allowing the shutter gate to remain on during integration, there is additional time for the photodiode to transfer the charge to the storage node. Consequently, the physical size of the shutter gate can be decreased. The pixels of the three exemplary embodiments ( FIGS. 2-11 ) may be used to form a pixel array 200 for use in an imaging device 908 ( FIG. 1 ). [0052] FIG. 12 shows a processor system 900 , which includes an imaging device 908 employing pixels constructed in accordance with any of the exemplary embodiments ( FIGS. 2-11 ) of the invention. The imager device 908 may receive control or other data from system 900 . System 900 includes a processor 902 having a central processing unit (CPU) that communicates with various devices over a bus 904 . Some of the devices connected to the bus 904 provide communication into and out of the system 900 ; an input/output (I/O) device 906 and imager device 908 are such communication devices. Other devices connected to the bus 904 provide memory, illustratively including a random access memory (RAM) 910 , hard drive 912 , and one or more peripheral memory devices such as a floppy disk drive 914 and compact disk (CD) drive 916 . The imager device 908 may be constructed as shown in FIG. 1 with the pixel array 200 having the characteristics of the invention as described above in connection with FIGS. 2-11 . The imager device 908 may, in turn, be coupled to processor 902 for image processing, or other image handling operations. Examples of processor based systems, which may employ the imager device 908 , include, without limitation, computer systems, camera systems, scanners, machine vision systems, vehicle navigation systems, video telephones, surveillance systems, auto focus systems, star tracker systems, motion detection systems, image stabilization systems, and others. [0053] The devices described above illustrate typical devices of many that could be used. The above description and drawings illustrate embodiments, which achieve the objects, features, and advantages of the present invention. However, it is not intended that the present invention be strictly limited to the above-described and illustrated embodiments. Any modifications, though presently unforeseeable, of the present invention that come within the spirit and scope of the following claims should be considered part of the present invention.

Description

Topics

Download Full PDF Version (Non-Commercial Use)

Patent Citations (28)

    Publication numberPublication dateAssigneeTitle
    US-5523570-AJune 04, 1996Loral Infrared & Imaging Systems, Inc.Double direct injection dual band sensor readout input circuit
    US-5751005-AMay 12, 1998Raytheon CompanyLow-crosstalk column differencing circuit architecture for integrated two-color focal plane arrays
    US-6043478-AMarch 28, 2000Industrial Technology Research InstituteActive pixel sensor with shared readout structure
    US-6091449-AJuly 18, 2000Kabushiki Kaisha ToshibaMOS-type solid-state imaging apparatus
    US-6107655-AAugust 22, 2000Eastman Kodak CompanyActive pixel image sensor with shared amplifier read-out
    US-6160281-ADecember 12, 2000Eastman Kodak CompanyActive pixel sensor with inter-pixel function sharing
    US-6233013-B1May 15, 2001Xerox CorporationColor readout system for an active pixel image sensor
    US-6243134-B1June 05, 2001Intel CorporationMethod to reduce reset noise in photodiode based CMOS image sensors
    US-6317154-B2November 13, 2001Intel CorporationMethod to reduce reset noise in photodiode based CMOS image sensors
    US-6352869-B1March 05, 2002Eastman Kodak CompanyActive pixel image sensor with shared amplifier read-out
    US-6423994-B1July 23, 2002Eastman Kodak CompanyActive pixel sensor with inter-pixel function sharing
    US-6466266-B1October 15, 2002Eastman Kodak CompanyActive pixel sensor with shared row timing signals
    US-6486913-B1November 26, 2002Intel CorporationPixel array with shared reset circuitry
    US-6522357-B2February 18, 2003Intel CorporationMethod and apparatus for increasing retention time in image sensors having an electronic shutter
    US-6552323-B2April 22, 2003Eastman Kodak CompanyImage sensor with a shared output signal line
    US-6697114-B1February 24, 2004Foveon, Inc.Triple slope pixel sensor and arry
    US-6731335-B1May 04, 2004Hyundai Electronics Industries Co., Ltd.CMOS image sensor having common outputting transistors and method for driving the same
    US-6750912-B1June 15, 2004Ess Technology, Inc.Active-passive imager pixel array with small groups of pixels having short common bus lines
    US-6759641-B1July 06, 2004Rockwell Scientific Licensing, LlcImager with adjustable resolution
    US-6867806-B1March 15, 2005Taiwan Advanced Sensors CorporationInterlace overlap pixel design for high sensitivity CMOS image sensors
    US-7045754-B2May 16, 2006Omnivision Technologies, Inc.Hybrid charge coupled CMOS image sensor having an amplification transistor controlled by a sense node
    US-7053947-B2May 30, 2006Samsung Electronics Co., Ltd.Methods for improving sensitivity of CMOS active pixel sensors
    US-7064362-B2June 20, 2006Stmicroelectronics S.A.Photodetector of an image sensor
    US-7081608-B2July 25, 2006Micron Technology, Inc.Pixel with differential readout
    US-7116367-B2October 03, 2006Canon Kabushiki KaishaSolid-state image pickup apparatus having a reset transistor controlled by an output line
    US-7238926-B2July 03, 2007Eastman Kodak CompanyShared amplifier pixel with matched coupling capacitances
    US-7244918-B2July 17, 2007Micron Technology, Inc.Method and apparatus providing a two-way shared storage gate on a four-way shared pixel
    US-7250970-B2July 31, 2007Canon Kabushiki KaishaImage pickup apparatus

NO-Patent Citations (0)

    Title

Cited By (67)

    Publication numberPublication dateAssigneeTitle
    US-7538304-B2May 26, 2009Aptina Imaging CorporationReducing noise in an imager by sampling signals with a plurality of capacitances connected to an output line
    US-2008062290-A1March 13, 2008Tower Semiconductor Ltd.Color Pattern And Pixel Level Binning For APS Image Sensor Using 2x2 Photodiode Sharing Scheme
    US-9819882-B2November 14, 2017Caeleste CvbaGlobal shutter high dynamic range sensor
    WO-2009133967-A2November 05, 2009Canon Kabushiki KaishaSolid-state imaging apparatus
    US-2017111603-A1April 20, 2017Semiconductor Components Industries, LlcImage sensor pixels having dual gate charge transferring transistors
    US-8072520-B2December 06, 2011Micron Technology, Inc.Dual pinned diode pixel with shutter
    US-2006044243-A1March 02, 2006Jeffrey RysinskiDual pinned diode pixel with shutter
    US-2010208096-A1August 19, 2010Nobuhiro TakedaImage capturing apparatus
    US-7924333-B2April 12, 2011Aptina Imaging CorporationMethod and apparatus providing shared pixel straight gate architecture
    US-2015070588-A1March 12, 2015Himax Imaging, Inc.Imaging processing circuit for generating and storing updated pixel signal in storage capacitor before next operating cycle
    US-2011157441-A1June 30, 2011Canon Kabushiki KaishaSolid state image pickup device and camera
    US-8698935-B2April 15, 2014Canon Kabushiki KaishaSolid-state image pickup device and camera having arrayed pixels including amplifying units
    US-8625010-B2January 07, 2014Canon Kabushiki KaishaSolid-state imaging apparatus with each pixel including a photoelectric converter portion and plural holding portions
    US-8149312-B2April 03, 2012Intellectual Ventures Ii LlcCMOS image sensor with shared sensing node
    US-9728574-B2August 08, 2017Asml Netherlands B.V., Carl Zeiss AgCMOS image sensor with shared sensing node
    US-2009237540-A1September 24, 2009Micron Technology, Inc.Imager method and apparatus having combined gate signals
    US-7642498-B2January 05, 2010Aptina Imaging CorporationCapacitor multipler circuits and the applications thereof to attenuate row-wise temporal noise in image sensors
    US-2005128324-A1June 16, 2005Takafumi Kishi, Nobuhiro TakedaImage sensing apparatus and method of controlling same
    US-8625017-B2January 07, 2014Intellectual Ventures Ii LlcCMOS image sensor with shared sensing mode
    US-2016165159-A1June 09, 2016Qualcomm IncorporatedSolid state image sensor with enhanced charge capacity and dynamic range
    WO-2006130519-A3February 01, 2007Eastman Kodak Co, Robert Michael Guidash, Ravi Mruthyunjaya, Weize XuPixel d'amplificateur partage presentant des capacites de couplage appariees
    US-8482642-B2July 09, 2013Micron Technology, Inc.Dual pinned diode pixel with shutter
    US-2009141155-A1June 04, 2009International Business Machines CorporationHigh dynamic range imaging cell with electronic shutter extensions
    US-9083908-B2July 14, 2015Canon Kabushiki KaishaSolid-state imaging apparatus with each pixel including a photoelectric conversion portion and plural holding portions
    US-2011007196-A1January 13, 2011Canon Kabushiki KaishaSolid-state imaging apparatus
    US-7800675-B2September 21, 2010Aptina Imaging CorporationMethod of operating a storage gate pixel
    US-8233071-B2July 31, 2012Canon Kabushiki KaishaImage capturing apparatus comprising image sensor and plurality of pixels with simultaneous transfer of pixel electric charge from a first to an oppositely arranged second storage device
    US-8203629-B2June 19, 2012Canon Kabushiki KaishaImage sensing apparatus and correction method
    US-7948535-B2May 24, 2011International Business Machines CorporationHigh dynamic range imaging cell with electronic shutter extensions
    US-2010182469-A1July 22, 2010Sony CorporationImage sensor
    US-2010090091-A1April 15, 2010Societe Francaise De Detecteurs Infranrouges-SofradirMethod and device for reading electrical charges produced by a photo-detector, and detector comprising such devices
    US-2007035649-A1February 15, 2007Micron Technology, Inc.Image pixel reset through dual conversion gain gate
    US-2006044437-A1March 02, 2006Joey ShahMethod of operating a storage gate pixel
    US-8253810-B2August 28, 2012Aptina Imaging CorporationMethod, apparatus and system for image stabilization using a single pixel array
    US-2010238334-A1September 23, 2010Sony CorporationSolid-state imaging device, method of manufacturing the same, method of driving the same, and electronic apparatus
    US-9111837-B2August 18, 2015Sony CorporationImage sensor
    US-8792034-B2July 29, 2014Sony CorporationSolid-state imaging device with charge transfer transistor on different substrates
    WO-2007126601-A3February 07, 2008Micron Technology Inc, John LaddRéduction du bruit dans un dispositif de formation d'images
    WO-2006130519-A2December 07, 2006Eastman Kodak CompanyShared amplifier pixel with matched coupling capacitances
    US-2008224186-A1September 18, 2008International Business Machines CorporationHigh Dynamic Range Imaging Cell With Electronic Shutter Extensions
    WO-2007126601-A2November 08, 2007Micron Technology, Inc.Reducing noise in an imager
    US-2016219236-A1July 28, 2016Kabushiki Kaisha ToshibaSolid-state image pickup device
    US-9774801-B2September 26, 2017Qualcomm IncorporatedSolid state image sensor with enhanced charge capacity and dynamic range
    US-8179463-B1May 15, 2012On Semiconductor Trading Ltd.Image sensor with shared node
    US-7773138-B2August 10, 2010Tower Semiconductor Ltd.Color pattern and pixel level binning for APS image sensor using 2×2 photodiode sharing scheme
    WO-2009133967-A3December 30, 2009Canon Kabushiki KaishaSolid-state imaging apparatus
    US-2009128991-A1May 21, 2009Micron Technology, Inc.Methods and apparatuses for stacked capacitors for image sensors
    US-8283618-B2October 09, 2012Societe Francaise De Detecteurs Infrarouges-SofradirMethod and device for reading electrical charges produced by a photo-detector, and detector comprising such devices
    WO-2007021626-A3August 02, 2007Micron Technology Inc, Jeffrey A MckeeImage pixel reset through dual conversion gain gate
    US-8441558-B2May 14, 2013Canon Kabushiki KaishaSolid state image pickup device and camera having arrayed pixels including amplifying units
    US-2016360127-A1December 08, 2016Caeleste CvbaGlobal shutter high dynamic range sensor
    US-2008246539-A1October 09, 2008Zadeh Ali ECapacitor multipler circuits and the applications thereof to attenuate row-wise temporal noise in image sensors
    US-2008100728-A1May 01, 2008Canon Kabushiki KaishaImage sensing apparatus and correction method
    CN-101273619-BFebruary 15, 2012普廷数码影像控股公司通过双重转换增益栅极复位的图像像素
    US-2009046189-A1February 19, 2009Micron Technology, Inc.Method and apparatus providing shared pixel straight gate architecture
    WO-2016089551-A1June 09, 2016Qualcomm IncorporatedCapteur d'image à semi-conducteur avec capacité de charge et plage dynamique améliorées
    US-2006273240-A1December 07, 2006Eastman Kodak CompanyShared amplifier pixel with matched coupling capacitances
    US-7719590-B2May 18, 2010International Business Machines CorporationHigh dynamic range imaging cell with electronic shutter extensions
    US-2014312451-A1October 23, 2014Sony CorporationSolid-state imaging element, manufacturing method, and electronic device
    US-2005151867-A1July 14, 2005Hiroshige Goto, Ikuko InoueSolid-state image pickup device with CMOS image sensor having amplified pixel arrangement
    JP-2015142114-AAugust 03, 2015キヤノン株式会社, Canon Inc固体撮像装置
    US-2006170804-A1August 03, 2006Magnachip Semiconductor Ltd.CMOS image sensor with shared sensing node
    CN-101410982-BJuly 21, 2010普廷数码影像控股公司降低成像器中的噪音
    US-2009147091-A1June 11, 2009Micron Technology, Inc.Method, apparatus and system for image stabilization using a single pixel array
    US-7675559-B2March 09, 2010Canon Kabushiki KaishaImage sensing apparatus having a two step transfer operation and method of controlling same
    US-7238926-B2July 03, 2007Eastman Kodak CompanyShared amplifier pixel with matched coupling capacitances
    KR-100940708-B1February 08, 2010앱티나 이미징 코포레이션Image pixel reset through dual conversion gain gate